? semiconductor components industries, llc, 2012 october, 2012 ? rev. 0 1 publication order number: EMI6183/d EMI6183 common mode filter with esd protection product description the EMI6183 is an integrated common mode filter in a 3x2, 6 ? bump, 0.4 mm pitch, csp form factor for the elimination of common mode noise in high speed data line applications such as usb2.0 and other lvds type applications. esd protection is integrated into the common mode filter for superior protection and significant part count reduction. features ? single integrated package for common mode filter (cmf) and esd protection for high speed data lines ? high differential mode bandwidth cutoff frequency for best signal integrity ? 3 x 2, 6 ? bump, 0.4 mm pitch csp ? provides esd protection to iec61000 ? 4 ? 2 level 4, 8 kv contact discharge at external pins and stand ? alone c2 pin ? provides esd protection to iec61000 ? 4 ? 2 level 1, 2 kv contact discharge at internal pins ? low channel input capacitance ? coated for improved reliability at assembly ? these devices are pb ? free and are rohs compliant ii packaging applications ? high speed differential data lines ? usb2.0 ? lvds http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information simplified schematic pin connections wlcsp6 case 567ga 61 = specific device code a = assembly location y = year w = work week = pb ? free package marking diagram 61 ayw
EMI6183 http://onsemi.com 2 ordering information device package part marking shipping ? EMI6183fctbg 3 x 2, 6 ? bump csp 61 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. pin description pin name type parameter a1 i/o cmf channel 1+ to asic (internal pin) a2 i/o cmf channel 1+ to connector (external pin) b1 i/o cmf channel 1 ? to asic (internal pin) b2 i/o cmf channel 1 ? to connector (external pin) c1 gnd ground c2 id id pin for esd protection (external pin) maximum ratings (t a = 25 c unless otherwise stated) parameter symbol rating unit esd discharge iec61000 ? 4 ? 2 contact discharge v pp 8.0 kv operating temperature range t op ? 40 to +85 c storage temperature range t stg ? 55 to +150 c maximum lead temperature for soldering purposes (1/8? from case for 10 seconds) t l 260 c dc current per line i line 100 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. electrical characteristics (note 1) parameter symbol test conditions min typ max unit maximum reverse working voltage v rwm 5.5 v breakdown voltage v b i r = 1 ma 6.0 v leakage current i leak v rwm = 3 v 10 300 na esd protection peak discharge voltage at a2, b2 & c2 a) contact discharge per iec61000 ? 4 ? 2 standard b) air discharge per iec61000 ? 4 ? 2 standard v esd (notes 2 and 3) 8.0 15 kv kv esd protection peak discharge voltage at a1 & b1 a) contact discharge per iec61000 ? 4 ? 2 standard b) air discharge per iec61000 ? 4 ? 2 standard v esd (notes 2 and 3) 2.0 2.0 kv kv tlp clamping voltage (see figure 6) v cl forward i pp = 8 a forward i pp = 16 a reverse i pp = ? 8 a reverse i pp = ? 16 a 11.58 15 ? 4.5 ? 8.8 v v v v resistance a1 to a2; b1 to b2 r ch 8.0 capacitance b2 to c1 c l1 at 1 mhz, v in = 0 v (note 2) 2.8 pf capacitance a2 to c1 c l2 at 1 mhz, v in = 0 v (note 2) 3.1 pf capacitance c2 to c1 c id at 1 mhz, v in = 0 v (note 2) 1.5 pf differential mode cut ? off frequency f 3db (note 4) 2.0 ghz common mode stop band attenuation f atten @ 800 mhz 21 db 1. all parameters specified at t a = 25 c unless otherwise specified. 2. these parameters guaranteed by design and characterization. 3. standard iec61000 ? 4 ? 2 with c discharge = 150 pf, r discharge = 300 . 4. above this frequency, appreciable common mode attenuation occurs at 50 source and 50 load termination.
EMI6183 http://onsemi.com 3 typical characteristics figure 1. differential mode attenuation vs. frequency figure 2. common mode attenuation vs. frequency 0 1.e+06 frequency (hz) (db) (db) frequency (hz) 0 1.e+07 1.e+08 1.e+09 1.e+10 1.e+06 1.e+07 1.e+08 1.e+09 1.e+10 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 ? 5 ? 10 ? 15 ? 20 ? 25 ? 30 ? 35 ? 40 ? 45 ? 50 b1 b2 a2 a1 emi6181 c2 c1 test configuration c1 EMI6183 c1 a1 b1 a2 b2 figure 3. normal (differential) mode test configuration c1 b2 a2 emi6181 b1 a1 EMI6183 c1 figure 4. application circuit application schematic
EMI6183 http://onsemi.com 4 transmission line pulse (tlp) measurements transmission line pulse (tlp) provides current versus voltage (i ? v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 5. tlp i ? v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10 s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 6 where an 8 kv iec61000 ? 4 ? 2 current waveform is compared with tlp current pulses at 8 and 16 a. a tlp curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. typical tlp i ? v curves for the EMI6183 are shown in figure 7. figure 5. simplified schematic of a typical tlp system dut v m i m l 10 m v c sw oscilloscope attenuator 50 coax cable 50 coax cable figure 6. comparison between 8 kv iec61000 ? 4 ? 2 and 8 a and 16 a tlp waveforms figure 7. positive and negative tlp waveforms 20 024 18 16 14 12 10 68 voltage (v) current (a) ? 20 0 ? 2 ? 4 ? 18 ? 16 ? 14 ? 12 ? 10 ? 6 ? 8 voltage (v) current (a) ? 18 ? 16 ? 14 ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 18 16 14 12 10 8 6 4 2 0
EMI6183 http://onsemi.com 5 esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to on semiconductor application notes and8307/d and and8308/d. iec61000 ? 4 ? 2 spec. level test voltage (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns 50 50 cable tvs oscilloscope esd gun figure 8. diagram of esd test setup
EMI6183 http://onsemi.com 6 figure 9. esd clamping voltage +8 kv per iec6100 ? 4 ? 2 (external to internal pin) figure 10. esd clamping voltage ? 8 kv per iec6100 ? 4 ? 2 (external to internal pin)
EMI6183 http://onsemi.com 7 package dimensions wlcsp6, 0.97x1.37 case 567ga issue a seating plane 0.03 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.50 millimeters a1 d 0.97 bsc e b 0.24 0.29 e 0.40 bsc 0.58 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 6x b 12 a b c 0.05 c a a1 a2 c 0.17 0.24 1.37 bsc pitch 0.25 6x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.03 c 2x top view side view bottom view note 3 a2 0.35 ref recommended a1 package outline e pitch optiguard coating on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 EMI6183/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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